The present invention relates generally to high-speed data interfaces and more particularly to circuitry for deskewing clock edges at high-speed data interfaces.
Modern computing and other electronic systems are handling more data at higher data rates than ever. Interfaces where one integrated circuit communicates with another integrated circuit, or one portion of an integrated circuit communicates with anther portion of an integrated circuit, are often bottlenecks that limit the ability of data to move around an electronic system. For example, interfaces to memory devices are one of the limiting function blocks in modern computing systems.
An example of such an interface is a double data-rate (DDR) memory interface, or more generally a multiple data-rate interface. A DDR interface is a synchronous (that is, clocked) interface where data is clocked on each edge of a clock signal. Specifically, alternating data bits in a DDR signal are clocked on the rising and falling edges of a clock signal.
Typically, data (a DQ signal) is provided along with a clock signal (a DQS signal) by a transmitting device or circuit. The clock signal has a rising or falling edge at each point where a transition in the data can occur. The receiving device or circuit shifts the clock signal by 90 degrees such that the edges of the clock are centered, that is midway, between edges of the data signal. By using two flip-flops, one clocked by rising edges and the other clocked by falling edges, the data signal can be recovered and errors and jitter in data signal edges have a minimized effect. This is referred to as centering the clock signal, or as window centering. Several things can conspire to skew rising and falling edges of clock signals such that data recovery is more error prone. For example, integrated and printed circuit board traces, circuits, and loads have inductive and capacitive effects that can cause the clock edges to skew. Further, circuits that generate and provide a clock signal may have mismatches between their ability to charge and discharge these parasitics and loads. These cause the rising and falling edges of the clock signal to become skewed.
Thus, what is needed are circuits, methods, and apparatus for deskewing clock rising and falling edges such that these clock edges are centered for a corresponding data signal.